Ansys|91国内精品视频|Matlab|91国内精品久久久|R语言培训课程班-91国内精品久久-曙海培训深圳成都南京苏州杭州

培訓(xùn)方式以講課和實(shí)驗(yàn)穿插進(jìn)行

第一階段 IC Compiler 1

Overview
The workshop is based on Synopsys? Lynx Compatible Reference Methodology (LCRM) flow:

• The CMM Data Setup unit covers how to load the files and libraries required by IC Compiler, as well as setting up scenarios for multi-corner multi-mode (MCMM) analysis and optimization.
• The Design Planning unit covers how to create a block-level floorplan, including macro placement and a power network, which results in acceptable routeability and timing throughout the flow.
• The Placement unit focuses on optimizing the placement and logic for timing, congestion, leakage power, and scan-chain ordering.
• The lock Tree Synthesis (CTS) unit covers controlling and building clock trees, optimizing clock power dissipation, and performing additional timing optimization.
• The outing unit covers routing of the clock nets, followed by signal routing and optimization, including redundant via insertion, antenna fixing, and crosstalk reduction.
• The Design for Manufacturability unit covers steps to improve yield and reliability, including wire spreading/widening, diode insertion, inserting filler cells, redundant via insertion, and signoff metal filling using IC Validator. The unit concludes by covering how to generate design data for final verification and validation, as well as converting the block into a hard macro for top-level integration.

Every lecture is accompanied by a comprehensive hands-on lab. Labs use the LCRM directory structure and scripts.

Objectives

At the end of this workshop you should be able to use IC Compiler to:

• Use the GUI to analyze the layout during the various design phases
• Perform and debug data setup to create an initial design cell which is ready for design planning and placement; This includes loading required files and libraries, creating a Milkyway design library, and applying common timing and optimization controls
• Create scenarios for MCMM timing, leakage power, and CTS optimization
• Create a non-hierarchical block-level floorplan for always-on single-voltage (non-UPF) designs that will be routable and will achieve timing closure
• Perform standard cell placement and related optimizations to minimize timing violations, congestion, and leakage power; Insert spare cells
• Analyze congestion maps and timing reports
• Apply any required CTS constraints, targets, and controls
• Perform pre-CTS power optimization to reduce clock tree power
• Execute the recommend clock tree synthesis and optimization flow
• Analyze clock tree and timing results post-CTS
• Perform routing setup to control DRC fixing, delay calculation, redundant via insertion, antenna fixing, and crosstalk reduction
• Route the clock nets
• Route the signal nets and perform post-route optimization
• Analyze and fix physical DRC and LVS violations
• Perform functional ECOs
• Perform design for manufacturability steps
• Generate output files required for final validation/verification

Course Outline

Unit 1

• Introduction
• MCMM Data Setup
• Design Planning

Unit 2

• Design Planning (Lab continued)
• Placement
• Clock Tree Synthesis

Unit 3

• Clock Tree Synthesis (Lab continued)
• Routing
• Design for Manufacturability
• Customer Support

第二階段 IC Compiler 2: Hierarchical Design Planning

Overview
The workshop teaches floorplan preparation for large and complex integrated circuits. You will learn to partition a design into hierarchical sub-blocks for implementation in IC Compiler. All the floorplan, constraint, and timing information required for implementation is created.

We begin with an initialized floorplan (learned in the IC Compiler 1 workshop). Next, standard cell and macro placement, using plan groups, guide the development of a physical hierarchy. Manipulation of the physical hierarchy is discussed in detail.

We then demonstrate a number of methods for improving the quality of the floorplan including: power network synthesis, in-place optimization, and budgeting. Finally, we create soft macro blocks suitable for place and route processing.

Hands-on labs for all course units use a hierarchical design allowing exploration of all aspects of virtual flat floorplanning.

Objectives

At the end of this workshop the student should be able to:

• Describe the IC Compiler Design Planning Virtual Flat Placement flow
• Manipulate the hierarchy and create plan groups using the Hierarchy Browser
• Perform Power Planning using IC Compiler's Power Network analysis and synthesis capabilities
• Describe the IC Compiler Design Planning Virtual Flat Placement flow
• Manipulate the hierarchy and create plan groups using the Hierarchy Browser
• Perform power planning using IC Compiler's power network analysis and synthesis capabilities
• Execute virtual flat placement and refine the plan groups
• Perform in-place optimization
• Perform plan-group-aware routing (PGAR) pin assignment on all blocks
• Perform design budgeting and generate block-level SDC files
• Generate ILM models for chip-level timing analysis and budgeting
• Define and develop effective time budgeting for place & route in IC Compiler

Course Outline

 

• Introduction & Overview
• Partition Top Level into Plan Groups
• Create Block Macros and Integrate Top