Ansys|91国内精品视频|Matlab|91国内精品久久久|R语言培训课程班-91国内精品久久-曙海培训深圳成都南京苏州杭州

第一階段

OVERVIEW

This workshop will enable the student to become proficient in using Astro to perform a timing-driven flow for placement, clock tree synthesis (CTS), routing and optimization to achieve timing closure for designs with moderate placement and routing challenges using a flat floorplan (chip or block). The main emphasis of the workshop is to learn a proven, effective flow that will achieve reasonable quality of results with fast time-to-market. The workshop covers the recommended flow steps for design set-up, floorplanning, timing set-up, placement, clock-tree synthesis, routing, optimization and design for manufacturability to achieve these results. Job aids will be provided to enable the student to recall and implement all the recommended steps back at the job.

This workshop will not cover advanced design closure features and flows such as: techniques of achieving timing closure on designs with complex or difficult placement, CTS and routing challenges, or signal integrity and power rail issues.

OBJECTIVES

At the end of this workshop the student will be able to:

• Describe key concepts and steps associated with automatic place&route
• Verify that all input data and information required to use Astro is available
• Implement a floorplan including macros
• Configure Astro for a timing driven flow
• Perform placement, clock-tree synthesis, routing and optimization in Astro, achieving timing closure for designs with moderate placement, CTS and routing challenges, emphasizing fast time to market
• Verify quality of results by analyzing timing and skew reports, congestion maps and other reports
• Interface to Synthesis and sign-off STA tools

AUDIENCE PROFILE

ASIC, back-end or layout design engineers with little or no experience in Apollo or Astro, who will be using Astro to perform automatic Place & Route.

PREREQUISITES

No previous experience with Astro or Apollo needed. Previous experience with non-Synopsys automatic Place & Route tool is helpful, but also not required.

COURSE OUTLINE

第一部分

Unit 1: Introduction to Place and Route

• Key concepts and steps associated with automatic place&route tools

Unit 2: Timing Setup

• Attaching TLU/TLU-Plus capacitance models
• Loading SDC constraints
• Configuring the timing setup panel
• Performing a "timing sanity check"

Unit 3: Placement

• Pre-place optimization
• Placement and post-place optimization
• Congestion analysis
• Handling scan chains
• Soft and hard blockages

第二部分

Unit 4: Clock Tree Synthesis

• Post-place optimization
• Clock tree synthesis and optimization
• Global Route?congestion

Unit 5: Design Setup

• Creating a library
• Attaching reference libraries
• Reading?and expanding the netlist
• Creating and binding a design cell
• Hierarchy preservation

Unit 6: Floorplanning (Lecture)

• Pad/Pin placement
• Power/ground grid creation
• Specifying the chip size and placement rows
• Macro placement
• Rectilinear block floorplanning

第三部分

Unit 6: Floorplanning (Lab)

?Unit 7: Routing

• Power/ground routing
• Clock net routing
• Global routing
• Track assignment
• Detail routing
• Search and repair
• Post- and in-route optimization and CTO

Unit 8: Design for Manufacturing

• Antenna fixing
• Metal slotting and filling
• DRC/LVS checking
• Writing files for Static Timing Analysis sign-off

第二階段

1.?Introduction to Physical Design

2.?Design and Timing Setup

3.?Placement

4.?Clock Tree Synthesis(CTS)

5.?Floorplanning

6.?RAM(Lecture)

7.?Routing

8.?Design for Manufacturing

9.?Customer Support