Ansys|91国内精品视频|Matlab|91国内精品久久久|R语言培训课程班-91国内精品久久-曙海培训深圳成都南京苏州杭州

嵌入式OS--4G手機(jī)操作系統(tǒng)

手機(jī)/網(wǎng)絡(luò)/動(dòng)漫游戲開發(fā)

嵌入式OS--WinCE

單片機(jī)培訓(xùn)

嵌入式硬件設(shè)計(jì)

嵌入式OS--VxWorks

PowerPC嵌入式系統(tǒng)/編譯器優(yōu)化

3G手機(jī)軟件測試、硬件測試

云計(jì)算、物聯(lián)網(wǎng)

開源操作系統(tǒng)Tiny OS開發(fā)

其他類

　

　

公益培訓(xùn)通知與資料下載

端海招聘啟示

　　培訓(xùn)班最新動(dòng)態(tài) 　

　　Encounter RTL Compiler培訓(xùn)班

Course Description

In this course, you explore the features of the Cadence? Encounter? RTL Compiler with global synthesis technology. You learn several techniques to constrain designs, run static timing analysis, evaluate datapath logic, optimize for low power, and interface with other tools.

Learning Objectives

After completing this course, you will be able to:

• Apply the recommended global synthesis flow using Encounter RTL Compiler.
• Navigate the design database and manipulate design objects.
• Constrain designs for global synthesis and run static timing analysis.
• Optimize RTL designs for timing and area using several strategies.
• Diagnose and analyze synthesis results.
• Use the extended datapath features of the compiler.
• Analyze and synthesize the design for low-power.
• Interface with other tools and place-and-route flows.

Course Agenda

Note that this course can be tailored to better meet your needs –?contact the Cadence training staff?for specifics.

Unit 1

• About this Course
• Introduction to Encounter RTL Compiler
• HDL Modeling
• Synthesis Flow
• Datapath Synthesis
• Optimization Strategies

Unit 2

• Low-Power Synthesis
• Interface to Other Tools
• Test Synthesis